R1 = 100Kohms
R2 = 47Kohms
R3 = 100Kohms
R4 ….. 10 = 2.2Kohms
R11 ….. 17 = 10Kohms
R18 ….. 24-25-26 = 220 ohmios
R25-26 = 1.2Kohms

C1 = 2200uF 25V
C2 = 100uF 25V
C3 = 18nF 100V
C4-5 = 10nF

D1 = 1N4148
Q1 a Q7 = BC550
Q8 a Q13 = BC560

IC1 = MM5314N ( Discontinue, National Semiconductor)

GR1 = 4X1N4002
T1 = 220V AC/12V 1A
DS1 a DS7 = Display Common Anodo

Datasheet document for digital clock IC MM5314N can be accessed here:
http://www.datasheetspdf.com/PDF/MM5314N/514207/1

Digital Tachometer Mainboard Scheme:

Digital Tachometer Front Display Scheme:

The digital RPM meter / tachometer comprises a motherboard and separate display board with a matching facia plate to provide a professional looking finish.

Digital Tachometer Specifications

• Range: 100 – 9900 revolutions/minute
• 2 digit display showing hundreds and Thousands of rPM’s (x100)
• Easy calibration
• Suitable for 2 and 4 stroke with Any number of cylinders
• Suitable for contact breaker or electronic ignition systems
• Contact breaker debounce circuit
• Resolution: 100 RPM
• Adjustable brightness
• Power supply: 10 – 15VDC / 200mA

The kit for this circuit is available, you may purchase the kit at quasarelectronics.co.uk.
Download the manual book about this circuit include the part list and how to assemble this circuit:

Digital RPM Meter_k2625

The above simple circuit design can be utilized as an accurate stopwatch to count up to 100 seconds with a determination of 0.01 second or up to 1000 seconds with a determination of 0.1 second. This stop-watch might be utilized for sports, games and other comparable different exercises.

A 1MHz crystal produce stable frequency which is divided by two stages of 74390 ICs (dual decade counter) and another stage employing 7490 (decade counter) IC to obtain a final frequency of 100 Hz or 10 Hz. Because of the usage of crystal, the final frequency will be very accurate.

The output of IC4 (7490) is counted and displayed using IC5 74C926 (4-digit counter with multiplexed 7-segment LED driver). Due to multiplexed display the power consumption is very low. Switch S2 (2-pole, 2-way) is utilized to select appropriate input frequency and corresponding decimal point position to display up to either 99.99 seconds or 999.9 seconds maximum count. The switch S1 and S2 is push button type.

For proper operation of this stopwatch circuit, the first is by do “reset” by press the switch S3 and then operate the switch S2, according to the resolution/range you choosed (0.1 sec. or 0.01 sec.)/(100 seconds or 1000 seconds). Then to start the time counting, just press switch S1. To stop counting, press switch S1 again. The counting will be stopped and the 7 segment LED display will show the correct time elapsed since the start of counting (the first time switch S1 pressed).

Here is the circuit diagram of stereo digital volume control. This circuit could possibly be applied for upgrading your manual volume management within a stereo amplifier circuit. In this particular circuit, push-to-on switch S1 controls the forward (volume enhance) operation of the two channels while a identical switch S2 controls reverse (volume reduce) operation of the two channels.

In this digital volume control circuit, the IC1 timer 555 is set up as an astable flip-flop to deliver low-frequency pulses to up/down clock input pins of pre-setable up/down counter 74LS193 (IC2) through push-to-on switches S1 and S2. To adjust the pulse width of pulses from IC1, you may possibly replace the timing resistor R1 by using a variable resistor.

Operation of switch S1 (up) triggers the binary output to increment while operation of S2 (down) triggers the binary output to decrement. The highest count being 15 (all outputs logic 1) and lowest count being 0 (all outputs logic 0), it outcomes in highest and lowest volume respectively.

The active high outputs A, B, C and D of the counter are utilized for controlling two quad bi-polar analogue switches in each of the two CD4066 ICs (IC3 and IC4). The two of the output bits, when high, short a part of the resistor network comprising series resistors R6 thru R9 for one channel and R10 thru R13 for the other channel, and thus manage the output of the audio signals being fed towards the inputs of stereo amplifier circuit module. Push-to-on switch S3 is utilized for resetting the output of counter to 0000, and thus turning the volume of both of those channels to the lowest level.

The above diagram is a hierachical priority encoder circuit. Described on wikipedia, priority encoder is a electronic circuit or algorithm that compresses multiple binary inputs into a smaller number of outputs. The output of a priority encoder is the binary representation of the ordinal number starting from zero of the most significant input bit. They are often used to control interrupt requests by acting on the highest priority request.”

Anormal priority encoder encodes only the highest-order data line. But in many situations, not only the highest but the second-highest priority information is also needed. The circuit presented here encodes both the highest-priority information as well as the second-highest priority information of an 8-line incoming data. The circuit uses the standard octal priority encoder 74148 that is an 8-line-to-3-line (4-2-1) binary encoder with active-“low” data inputs and outputs.

The first encoder (IC1) generates the highest-priority value, say, F. The active “low” output (A0, A1, A2) of IC1 is inverted by gates N9 through N11 and fed to a 3-line-to-8-line decoder (74138) that requires active-“high” inputs. The decoded outputs are active-“low”. The decoder identifies the highest-priority data line and that data value is cancelled using XNOR gates (N1 through N8) to retain the second-highest priority value that is generated by the second encoder.

To understand the logic, let the incoming data lines be denoted as L0 to L7. Lp is the highest-priority line (active-“low”) and Lq the second-highest priority line (active-“low”). Thus Lp=0 and Lq=0. All lines above Lp and also between Lp and Lq (denoted as Lj) are at logic 1. All lines below Lq logic state are irrelevant, i.e. “don”t care”. Here p is the highest-priority value and q the second-highest-priority value. (Obviously, q has to be lower than p, and the minimum possible value for p is taken as “1”.)

Priority encoder IC1 generates binary output F2, F1, F0, which represents the value of p in active-“low” format. The complemented F2, F1, and F0 are applied to 3-line-to-8-line (one out of eight outputs is active-“low”) decoder 74138. Let the output lines of 74138 be denoted as M0 through M7. Now only one line is active-“low” among M0 through M7, and that is Mp (where the value of p is explained as above). Therefore the logic level of line Mp is “0” and that of all other M lines “1”.

The highest-priority line is cancelled using eight XNOR gates as shown in the figure. Let the output lines from XNOR gates be N0 through N7. Consider inputs Lp and Mp of the corresponding XNOR gate. Since Mp = 0 and also Lp = 0, the output of this XNOR gate is Np = complement of Lp = 1. All other L”s are not changed because the corresponding M”s are all 1″s. Thus data lines N0 through N7 are same as L0 through L7, except that the highest-priority level in L0 through L7 is cancelled in N0 through N7.

The highest-priority level in N0 through N7 is the second-highest priority leftover from L0 through L7, i.e. Nq=0 and Nj=1 for q to priority encoder 2 (IC3) to generate S2, S1, S0, which represent q. Thus the second-highest priority value is extracted. Through cascading one can recover the third-highest priority, and so on.

For example, let L0 through L7 = X X X 0 1 1 0 1. Here the highest “0” line is L6 and the next highest is L3 (X denotes “don”t care”). Thus p=6 and q=3. Now the active-“low” output of the first priority encoder will be F2 F1 F0 = 0 0 1. The input to 74138 is 1 1 0 and it outputs M0 through M7 = 1 1 1 1 1 1 0 1. Since M6=0, only L6 is complemented by XNOR gates.

Thus the outputs of XNORs are N0 through N7 = X X X 0 1 1 1 1. Now N3=0 and the highest priority for “N” is 3. This value is recovered by priority encoder 2 (IC3) as S2 S1 S0 = 1 0 0.

This is the design diagram of electronic jam. This jam circuit can be implemented in quiz contests in which any participator who pushes his switch (button) prior to the other participants, will get the first opportunity to answer a question. The circuit provided right here allows up to eight participants with each one assigned a unique number (1 to 8). The display will show the number of the contestant pushing his button prior to the others. Concurrently, a buzzer will also sound. Both of those, the display and also the buzzer need to be reset manually working with a general reset switch.

At first, when reset switch S9 is briefly pushed and released, all outputs of 74LS373 (IC1) transparent latch go “high” because all of the input data lines are returned to Vcc by way of resistors R1 through R8. All eight outputs of IC1 are joined to inputs of priority encoder 74LS147 (IC2) as well as 8-input NAND gate 74LS30 (IC3). The output of IC3 thus becomes logic 0 which, after inversion by NAND gate N2, is implemented to latch-enable pin 11 of IC1. With all input pins of IC2 becoming logic 1, its BCD output is 0000, that is put on 7-segment decoder/driver 74LS47 (IC6) right after inversion by hex inverter gates within 74LS04 (IC5). Therefore, on reset the display will show 0.

When any one of the push-to-on switches-S1 through S8-is pushed, the affiliated output line of IC1 is latched at logic 0 level and also the display signifies the number associated with the certain switch. Simultaneously, output pin 8 of IC3 gets high, that triggers outputs of the two gates N1 and N2 to proceed to logic 0 condition. Logic 0 output of gate N2 inhibits IC1, and thus pushing of any other switch S1 through S8 doesn’t have any result. As a result, the contestant who pushes his button first, jams the display to show only his number. In the unlikely event of simultaneous pushing (within few nano-seconds difference) of more than one switch, the higher priority number (switch no.) is going to be shown. Concurrently, the logic 0 output of gate N1 drives the buzzer via PNP transistor BC158 (T1). The buzzer also the display could be reset (to display 0) by momentary pressing of reset switch S9 in order that up coming round may get started.

You may design this electronic jam circuit similar to the following preview:

This is the 1Hz clock generator circuit with Chip On Board (COB). Commonly, the circuits to produce 1Hz clock for digital clock and counter circuits applications implement ICs in conjunction with a crystal and trimmer capacitors, etc. Even so, equivalent or improved accuracy could be obtained working with a chip-on-board (COB) device found inside a digital clock, that is readily offered in the marketplace. This COB includes IC, capacitors and quartz crystal, etc that are installed on its surface. It operates on 1.4 volt DC supply. This COB could be utilized to get 1Hz clock.

Resistor R1, capacitor C3, diodes D1 and D2 shown in the circuit change 5V DC into 1.4V DC. A ?Hz clock is accessible at terminals A and B with a phase variation of 90o. The two outputs, are put together making use of capacitors C1 and C2 to acquire a complete 1Hz clock. This 1Hz clock pulse features a extremely low amplitude of the order of a few milli-volts which can’t be utilized to drive the digital circuits instantly. This low-level voltage is amplified several times by operational amplifier (op-amp) IC CA3140.

The op-amp CA3140 is connected in a non-inverting mode, and its gain is set by resistors R4 and R3. Capacitor C2 minimizes the AC gain and undesired stray pick-up and thus increases stability of the circuit.

The input impedance of IC CA3140 is extremely high and thus there is absolutely no drop at the input when 1Hz clock signal of low level is connected across its input terminals from the COB. Amplified 1Hz clock pulse is accessible at its output pin 6, that is further amplified by transistors T1 and T2 to drive the digital clocks and timers.

Preset VR1 is offset null control utilized to adjust accurate 1Hz pulse at the output terminal “E”. Connect one LED in series with 220-ohm resistor between the terminal “E” and ground and alter preset VR1 till the LED blinks once every second. When utilizing the COB, affix the same on a general-purpose PCB working with rubber based adhesive and solder the terminals neatly making use of thin single-strand wire.

Note: The COBs utilized in different watches may differ somewhat in their settings. But by trial-and error one can always find out the proper points corresponding to points A, B, C and D.

Download 1Hz clock generator with Chip On Board (COB) circuit in PDF document (include the configuration of COB):

1 Hz Clock Generator Circuit Document

1 file(s) 84.93 KB

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This is a very simple analoque to digital converter circuit based on 8-bit analog-to-digital converter ADC0808. Typically analogue-to-digital converter (A/D Converter / ADC) requires interfacing through a microprocessor to convert analogue information into digital format. This needs extra hardware and appropriate software, resulting in more complexity and hence the total amount of cost.

The circuit of Analogue to Digital converter shown here is configured around ADC0808, getting rid of the utilization of a microprocessor. The ADC0808 is definitely an 8-bit A/D converter, that has data output lines D0-D7. It operates on the principle of successive approximation. It features a total of eight analogue input channels, out of which any one can be chosen working with address lines A, B and C. Right here, in this case, input channel IN0 is chosen by grounding A, B and C address lines.

Typically the control signals ALE (address latch enable), EOC (end of conversion), OE (output enable) and SC (start conversion) are interfaced by means of a microprocessor. Even so, the circuit shown
right here is constructed to operate in its continuous mode without working with any microprocessor. Therefore the input control signals ALE and OE, getting active-high, are tied to Vcc (+5 volts). The input control signal SC, getting active-low, initiates start of conversion at falling edge of the pulse, whereas the output signal EOC becomes high after completion of conversion (digitisation). This EOC output is coupled to SC input, where falling edge of EOC output acts as SC input to direct the ADC to begin the subsequent conversion.

Since the conversion starts, EOC signal goes high. At next clock pulse EOC output again goes low, and hence SC is enabled to get started on the next conversion. Thus, it delivers continuous 8-bit digital output corresponding to instantaneous value of analogue input. The optimum level of analogue input voltage ought to be properly scaled down below positive reference (+5V) level.

The ADC0808 IC needs clock signal of normally 550 kHz, which can be simply produced from an astable multivibrator constructed applying 7404 inverter gates. In order to visualise the digital output, the row of eight LEDs (LED1 through LED8) have been utilized, wherein every single LED is connected to respective data output lines D0 through D7. Considering that A/D Converter runs in the continuous mode, it shows digital output as soon as analogue input is applied. The decimal equivalent digital output value D for a provided analogue input voltage Vin can be calculated from below relationship:

D = Vin/Vref * 256

Download Area

ADC0808 Datasheet:

ADC0808/ADC0809 Datasheet Document

1 file(s) 267.41 KB

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ADC0808 – Simple Analoque to Digital Converter in PDF file:

Analog to Digital Converter Circuit Document

1 file(s) 52.81 KB

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About Arduino UNO:
The Arduino Uno is really a microcontroller board based on the ATmega328. It has 14 digital input/output pins (of which 6 may be employed as PWM outputs), 6 analog inputs, a 16 MHz crystal oscillator, a USB connection, a power jack, an ICSP header, along with a reset button. It contains every little thing needed to support the microcontroller; just connect it to a laptop or computer having a USB cable or power it with a AC-to-DC adapter or battery to obtain began.

The UNO differs from all preceding boards in that it does not use the FTDI USB-to-serial driver chip. Instead, it functions the Atmega8U2 programmed as a USB-to-serial converter.

“UNO” means one in Italian and is named to mark the upcoming release of Arduino 1.0. The Uno and version 1.0 is going to be the reference versions of Arduno, moving forward. The Uno will be the latest in a series of USB Arduino boards, along with the reference model for the Arduino platform; for a comparison with previous versions, see the index of Arduino boards.

Arduino UNO schematic download area

Download Arduino UNO: Arduino UNO schematic | Mirror File
Download EAGLE design: Arduino UNO schematic | Mirror File
Eagle files contain Arduino UNO schematic and board design

Circuit Notes:

• Excellent clock generator to drive 4017 type CMOS circuits.
• R1 = 10K to 10M, C1 = 100pF to 47uF.
• Fo is ? 1KHz when R1 = 100K and C1 = 10nF.
• You must use regulated 5V input voltage for 7400, while CMOS 4011 can be from 5 to 15V. Regulated power supply with LM7805 will be great to supply this circuit (with 7400).

Below images are the pin assignment for NAND Gate TTL IC 7400 and NAND Gate CMOS IC 4011: